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in the absence of confirmation by device specification sheets, sharp takes no responsibility for any defects that may occur in equipment using any sharp devices shown in catalogs, data books, etc. contact sharp in order to obtain the latest device specification sheets before using any sharp device. 1 description the LH155BA is an lcd driver with a built-in ram suitable for driving medium/small scale dot-matrix lcd panels, and which is capable of being directly connected to the bus line of a microcomputer. the LH155BA stores in the ram the 8-bit parallel or serial display data transferred from the microcomputer and generates lcd drive signals. since the LH155BA features a bit-map type lcd driver that one bit of data in the display ram corresponds to one dot in the lcd, there is a lot of freedom in displaying. the LH155BA has 128 segment outputs and 64 common outputs in a single chip, making it possible to create an lcd system with the fewest number of the chips. the LH155BA enables an lcd system for battery- operated, hand-carrying information equipment by securing lower power consumption and wider operating voltage range. features graphic display output pin : 64 x 128 pins segment display output pin : 3 x 12 pins icon display output pin : 1 x 1 pin lcd display by graphic display ram e normal mode : ram data "0" / not lighted, ram data "1" / lighted e reverse mode : ram data "1" / not lighted, ram data "0" / lighted display ram memory capacity e 128 x 64 = 8 192 bits (for graphic display) e 12 x 3 = 36 bits (for segment display) e 1 x 1 = 1 bit (for icon display) general 8-bit mpu interface : possible to directly connect 80-family and 68-family mpus to bus line possible to make serial interface ratio of display duty cycle : 1/16, 1/32, 1/48 or 1/64 (selectable by command) 128-bit automatic transfer from display ram to display data latch abundant command functions e display data read/write e setting up lcd alternating signal cycle e setting up display starting-line : per line e display on/off e display control of normal and reverse modes e increment control of display ram address e write control of read modifying e internal register read e power saving mode lcd drive power circuit e built-in booster circuit : two, three or four times voltage boost is possible e built-in voltage converter : generates lcd drive voltages (v 0 , v 1 , v 2 , v 3 and v 4 ) based on the boosted voltage e built-in power bias ratio : 1/7 or 1/9 bias (selectable by command) e built-in electronic volume : controllable in 16 steps e supply voltages logic system : +1.8 to +5.5 v lcd drive system : +4.0 to +14.0 v operating temperature : e30 to +85 ?c package : 260-pin tcp (tape carrier package) LH155BA LH155BA 128-segment and 64-common outputs lcd driver ic with a built-in ram
pin connections LH155BA 2 209 210 260 1 coms 0 coms 1 coms 2 segs 0 segs 1 icon 2 icon 1 com 31 com 30 segs 11 segs 10 com 63 com 62 com 33 com 32 seg 127 seg 126 seg 125 seg 2 seg 1 seg 0 com 0 com 1 chip surface v a v b v c v d v r2 v r1 v out v ee3 svout v ee2 svr cap+ cap v ee v dd pmode exa cks ck v ss osci osco v ss m flm lp d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 rdb wrb scl sda p/s m86 m/s rs csb resb test v ss v 4 v 3 v 2 v 1 v 0 260-pin tcp top view note : doesn't prescribe tcp outline.
block diagram LH155BA 3 50 49 242 ck cks osco 240 osci 244 exa 237 m flm 235 lp 218 csb 219 rs 220 m/s 221 m86 226 rdb 225 wrb 217 resb 222 p/s 223 sda 224 scl 216 test 234 d 7 233 d 6 232 d 5 231 d 4 230 d 3 229 d 2 228 d 1 227 d 0 215 v ss v ss v ss 238 241 249 cap+ 248 cape 251 v ee2 253 v ee3 247 v ee 245 pmode 252 svout 254 v out 255 v r1 v r2 250 svr 246 v dd 257 v d 258 v c 259 v b 210 v 0 260 v a 3 coms 0 coms 2 56 segs 0 17 segs 11 seg 127 com 0 seg 0 com 31 com 32 209 1 com 63 icon 1 2 icon 2 segment driver segment common driver shift register data latch dc-dc converter lcd power supply electronic volume y address register y address counter icon i/o buffer mpu interface osc display timing generator 213 v 3 212 v 2 211 v 1 214 v 4 18 178 243 239 236 177 x address decoder x address counter x address register y address decoder display line counter line address decoder display line register display ram 64 x 128 bits (for graphic) 3 x 12 bits (for segment) ac conversion control bus holder i/o buffer command decoder register read control 256
4 LH155BA symbol 1. pin description 1.1. power supply pins i/o description v dd power supply power supply pin for logic, connected to +1.8 to +5.5 v. v ss power supply ground pin, connected to 0 v. v 0 v 1 v 2 v 3 v 4 v a v b v c v d power supply v 0 -v 4 for graphic display v a -v d for segment display bias power supply pins for lcd drive voltage. when using an external power supply, convert impedance by using resistance- division of lcd drive power supply or operational amplifier before adding voltage to the pins. when using the external power supply, maintain the following power supply conditions. v ss < v 4 < v 3 < v 2 < v 1 < v 0 , v ss 2 v d < v c < v b < v a when the power supply circuit is on at master operation, lcd drive voltages of v 0 to v 4 are generated by the internal booster circuit and voltage converter. when using segment display, input v a , v b , v c and v d level externally. when using the internal power supply, be sure to connect each capacitor between v 0 to v 4 , v a to v d , and v ss . 1.2. lcd power supply circuit pins symbol i/o description cap+ o connecting pin for the internal booster's capacitor + side. the capacitor is connected between cape and cap+. cape o connecting pin for the internal booster's capacitor e side. the capacitor is connected between cap+ and cape. v r1 v r2 i used as input pins for graphic display voltage converter. voltage must be input between the v ee and v out pins by voltage divided by resistors. v ee3 o connecting pin for the internal booster's capacitor + side. the capacitor is connected between v ss and v ee3 . v ee2 o connecting pin for the internal booster's capacitor + side. the capacitor is connected between v ss and v ee2 . voltage supply pin for generating boosted voltage in the internal booster circuit. usually the same voltage level as v dd . power supply v ee v out power supply/ o output pin of boosted voltage in the internal booster circuit. the capacitor must be connected between v ss and v out . non-connected. e svout non-connected. e svr pmode pin for controlling lcd power supply. a combination of pmode pin and on/off command of power supply (pon) enables selection of a specific drive operation. i
5 LH155BA 1.3. system bus pins symbol i/o description csb i chip selection input pin that decoded address bus signal is input. rs i distinguishes display ram data/commands of d 7 to d 0 data transferred from mpu. 0 : the data of d 7 to d 0 show the display ram data. 1 : the data of d 7 to d 0 show the command data. rdb (e) i in connecting to 80-family mpu : this rdb is a pin for connecting the rdb signal of 80-family mpu. when the signal enters in the "l" state, the data bus of this ic turns to the "output" state. in connecting to 68-family mpu : this rdb becomes a pin for connecting the enable clock signal of 68-family mpu. when the signal enters in the "h" state, the data bus of this ic turns to the "active" state. wrb (r/w) i in connecting to 80-family mpu : this wrb is a pin for connecting the wrb signal of 80-family mpu, and when wrb signal is "l", this pin is "active". the data bus signal is input at the rising edge of wrb signal. in connecting to 68-family mpu : this wrb becomes a pin for connecting the r/w signal of controlling read/write of 68-family mpu. r/w = "h" : read r/w = "l" : write i m86 mpu interface-type shift pin. m86 = "h" : 68-family interface m86 = "l" : 80-family interface fixed to either "h" or "l". sda i serial-data input pin at time of serial interface selection. scl i serial clock pin at time of serial interface selection. used to shift the sda data by using the rising edge of scl. used to convert into 8-bit data by using the 8th clock at the rising edge of scl in serial-to-parallel data processing. after data-transferring, or when making no access, be sure to set to "l". 8-bit bi-directional data bus, connected to 8-bit mpu data bus. i/o d 7 -d 0 initialized by setting to "l". the reset signals of the system are normally input. reset operation is performed in accordance with resb signal level. i resb used to shift between parallel interface and serial interface. p/s = "h" for parallel input. fix sda and scl pins to either "h" or "l". p/s = "l" for serial input. fix d 7 to d 0 pins to high-z, rdb and wrb pins to either "h" or "l". i p/s test i for testing. fix to "l". p/s chip selection data identification data read/write serial clock h csb rs d 7 -d 0 rdb, wrb e l csb rs sda write only scl
6 LH155BA symbol i/o description 1.4. lcd drive circuit signals lp i/o the latching signal of display data to count up the display line counter at the rising, and to output the lcd drive signals at the falling. m/s = "h" : output for master mode m/s = "l" : input for slave mode flm i/o i/o pin for lcd synchronous signals (first line marker). when flm pin is set to "h", the display starting line address is preset in the display line counter. m/s = "h" : output for master mode m/s = "l" : input for slave mode m i/o i/o pin for alternating signals of lcd drive output. m/s = "h" : output for master mode m/s = "l" : input for slave mode m/s i used to select either master or slave mode operation. fix to "h" or "l" at this pin. seg 0 -seg 127 o segment output pins for graphic display. according to the data of the display ram data, non-lighted at "0", lighted at "1" (normal mode) non-lighted at "1", lighted at "0" (reverse mode) and, by a combination of m signal and display data, one signal level among v 0 , v 2 , v 3 , and v ss is selected. m/s state osc p.s.circuit lp flm m h master enabled enabled output output output l slave disabled disabled input input input display ram data m signal normal mode reverse mode v 2 v 0 v 0 v 2 v 3 v ss v ss v 3 com 0 -com 63 o common output pins for graphic display. by a combination of the scanning data and m signals, one signal level among v 0 , v 1 , v 4 and v ss is selected. data h l h l m h h l l output level v ss v 1 v 0 v 4
7 LH155BA segment output pins for segment display. when executing segon command, it functions as segment output pins. common output pins for segment display. when executing segon command, it functions as common output pin. o coms 0 -coms 2 segs 0 -segs 11 o o icon 1 common output pin for icon display. when executing icon command, it functions as common icon display output pin. data output pin for icon display. when executing icon command, it functions as data icon display output pin. icon 2 o coms state seg on seg off display v ss segs state segon = "1" segon = "0" display v ss icon 1 state icon = "1" icon = "0" display v ss icon 2 state icon = "1" icon = "0" display v ss symbol i/o description * master clock : clock for oscillation circuit or external clock. symbol i/o description cks i selection input pin of display master clock at master mode. cks = "h" : input the external clock to ck pin. cks = "l" : the internal oscillation circuit by using osci and osco pins is used. input pin of display master clock at master mode. when using ck pin as an input of the master clock, fix osci pin to v ss . when using the internal oscillation circuit as the display master clock, fix ck pin to v ss . i ck 1.5. pins for oscillation circuit input pin of icon clock. i exa feedback-resistance connecting pin for the internal oscillation circuit. i o osci osco
8 LH155BA 1.6. input/output circuits i v dd v ss (0 v) to internal circuit fig. 1 input circuit applicable pins csb, rs, rdb, wrb, m86, m/s, p/s, sda, scl, exa, osci, ck, cks, pmode, resb, test i o v ss (0 v) v dd v dd v ss (0 v) output control signal output signal to internal circuit fig. 2 input/output circuit (1) applicable pins osco, flm, lp, m
LH155BA 9 to internal circuit v ss (0 v) i o v ss (0 v) v dd v dd v ss (0 v) output control signal output signal input control signal fig. 3. input/output circuit (2) applicable pins d 7 -d 0 v 0 v 0 v ss (0 v) v 1 /v 2 v ss (0 v) v 3 /v 4 v ss (0 v) output control signal 1 output control signal 3 output control signal 2 output control signal 4 o fig. 4. lcd drive output circuit (graphic display) applicable pins seg 0 -seg 127 , com 0 -com 63
10 LH155BA v a v a v ss (0 v) v b v ss (0 v) v c v d output control signal 1 output control signal 3 output control signal 2 output control signal 4 o applicable pins segs 0 -segs 11 , coms 0 -coms 2 output control signal 1 o output control signal 2 v ss (0 v) v dd v dd v ss (0 v) fig. 5. lcd drive output circuit (segment display) applicable pins icon 1 , icon 2 fig. 6. lcd drive output circuit (icon display) 2. functional description 2.1. mpu interface 2.1.1. interface type selection the LH155BA transfers data through 8-bit parallel i/o (d 7 to d 0 ) or serial data input (sda, scl). the selection between parallel interface and serial interface is made by setting the state of p/s pin to "h" or "l". when selecting serial interface, data-reading cannot be performed, but data-writing can. p/s i/f type csb rs rdb wrb m86 sda scl data h parallel csb rs rdb wrb m86 e e d 7 to d 0 l serial csb rs e e e sda scl e 2.1.2. parallel input the LH155BA can transfer data in parallel by directly connecting 8-bit mpu to the data bus when parallel interface is selected with p/s pin. as an 8-bit mpu, either 80-family mpu interface or 68-family mpu interface is selected with m86 pin. m86 mpu type csb rs rdb wrb data h 68-family mpu csb rs e r/w d 7 to d 0 l 80-family mpu csb rs rdb wrb d 7 to d 0
LH155BA 11 2.1.3. data identification the LH155BA can identify the data of 8-bit data bus by combinations of rs, rdb and wrb signals. rs 68-family r/w 80-family function rdb wrb 1 1 0 1 reads from internal register 1 0 1 0 writes to internal register 0 0 1 0 writes to display data ram 0 1 0 1 reads from display data ram 2.1.4. serial interface the serial interface of LH155BA can accept inputs of sda and scl in the chip selection state (csb = "l"). when not in the chip selection state, the internal shift register and counter are reset to their initial condition. serial data sda are input sequentially in order of d 7 to d 0 at the rising edge of serial clock (scl) and are converted into 8-bit parallel data (by serial to parallel conversion) at the rising edge of the 8th serial clock, being processed in accordance with the data. the identification whether the serial data inputs (sda) are display data or commands is judged by input to rs pin. rs = "l" : display data rs = "h" : commands after completing 8-bit data transferring, or when making no access, be sure to set serial clock input (scl) to "l". protection of sda and scl signals against external noise should be taken in actual wiring. to prevent the successive recognition errors of transferring data from external noise, release the chip selection state (csb = "h") at every completion of 8-bit data transferring. valid d 0 rs scl sda csb d 1 d 2 d 3 d 4 d 5 d 6 d 7 8 7 6 5 4 3 2 1
12 LH155BA data write operation n n n + 4 n + 1 n + 1 n + 2 n + 2 n + 3 n + 4 n + 3 d 7 -d 0 wrb internal bus holder wrb data read operation d 7 -d 0 wrb address set n address data read n address data read n + 1 address data read n + 2 address dummy read rdb n *** n n + 1 n + 2 2.2. access to display ram and internal register the LH155BA makes access to display ram, and internal register by data bus d 7 to d 0 , chip selection csb pin, display ram/register shifting rs pin, and read/write control rdb and wrb pins. when csb is at "h", it is in non-selective state and cannot access display ram and internal registers. when making access to them, set csb to "l". the access to either display ram or internal registers can be shifted by rs input. rs = "l" : display ram data rs = "h" : internal command register the data of 8-bit data bus d 7 to d 0 are written by write-operation after address setting through mpu. the timing of write is at the rising of wrb for 80- family mpu and at the falling of e for 68-family mpu respectively. write is internally processed by intermediately placing the bus holder in the internal data bus. during data writing from mpu, the data are temporally held in the bus holder, then they are written by the time of the next cycle. since the read sequence of display ram data is limited, note that when address set is made, the designated address data are not output to read command immediately after the address set, but are output when the second data are read, resulting in requiring one time dummy read. dummy read is always required one time after address set and write cycle.
13 LH155BA 2.3. read of internal register the LH155BA reads not only display ram, but also the internal registers. read addresses (0 h , 2 h -e h ) are allotted to each internal register. in reading the internal registers, the addresses of internal registers allotted to read are written in the registers for internal register read and then are read. wrb d 7 -d 0 rdb for register address set for register address set internal register data read internal register data read mm n n
LH155BA 14 00 h 01 h 02 h 03 h 04 h 05 h 06 h 07 h 08 h 00 h 0f h 3a h 3b h 3c h 3d h 3e h 3f h 3a h 3b h 3c h 3d h 3e h 3f h 00 h 01 h 02 h 03 h 04 h 05 h 06 h 07 h 08 h seg 127 seg 126 seg 125 seg 124 seg 123 seg 122 seg 121 seg 120 seg 7 seg 6 seg 5 seg 4 seg 3 seg 2 seg 1 seg 0 x address y address first line address 2.4. display mode the LH155BA has 3 display modes. one is for graphic display mode and one is for segment display mode and the other is for icon display mode. since 3 modes can be used independently by command, the suitable display mode can be selected to drive the device with minimum circuit for lower supply current operation. 2.4.1. graphic display mode this mode is built in 64 x 128 bits sram and 64- common x 128-segment output. graphic display's memory map is shown below. when standby mode and sleep mode, power supply circuit is stopped and output pin is specified v ss level. the memory for graphic display is accessed by 8 bits at one time. x address is from 00 h to 0f h and y address is from 00 h to 3f h .
15 LH155BA 2.4.2. segment display mode this mode enables 3 x 12 bits memory and 3 coms x 12 segs output. segment display's memory map is below. bias is fixed to 1/3. when display off, each output pin is specified v ss level. x address is from 00 h to 01 h , and y address is from 40 h to 42 h . segment display mode and graphic display mode are independent of each other. when using segment display mode, lower power operation is possible. when using slave mode, input clock for segment display at exa pin (500 hz : duty 50%), and this time, exa flag (e h register : see section 4.14. "power control (3) register set" ) must be fixed to "h". 40 h 41 h 42 h 00 h 01 h segs 11 segs 10 segs 9 segs 8 segs 7 segs 6 segs 5 segs 4 segs 3 segs 2 segs 1 segs 0 x address is 00 h -01 h , and y address is 40 h -42 h . segs 0 coms 0 coms 1 coms 2 segs 1 segs 2 segs 10 segs 11
16 LH155BA 2.4.3. icon display mode this mode enables 2 output pins for icon display and this mode can display 1 icon. source are v dd and v ss . since this mode is independent of other mode completely, when using this mode, lower power operation is possible. waveform of this mode is below. to display, use internal clock or external clock. when using external clock, input clock pulse to exa pin (120 hz : duty 50%). when using icon display and segment display, input 500 hz, duty 50% pulse. icon 1 v dd v dd icon 2 v ss v ss 2.5. display starting line register this register is for determining display starting line (usually the most upper line) corresponding to com 0 when displaying the display data ram. the register is also used in picture-scrolling. the 6-bit display starting address is set in this register by display starting line setting command. the register is preset every timing of flm signal variation in the display line counter. the line counter counts up being synchronized with lp input and generates line addresses which sequentially read out 128-bit data from display ram to lcd drive circuit. 2.6. addressing of display ram display ram consists of 128 x 64 bits memory, and enables access in 8-bit unit to an address specified by x address and y address from mpu. it is possible to set up the addresses x and y so that they can increment automatically with the address control register. the increment is made every time display ram is read or written from mpu. (see section 4. "command function" .) though the x direction side is selected by x address while the y direction side by y address, 10 h -ff h in the x address are inhibited and do not have the x address set in these addresses. in the y direction side, the 128-bit display data are internally read into the display data latch circuit at the rising of lp every one line cycle, and are output from the display data latch circuit at the falling of lp. 43 h -ff h in the y address are inhibited and do not have the y address set in these addresses. when flm signals being output in one frame cycle are at "h", the value in the display starting line register are preset in the line counter and the line counter counts up at the falling of lp signals. the display line address counter is synchronized with each timing signal of the lcd system to operate and is independent of address counters x and y.
LH155BA 17 2.7. display ram data and lcd one bit of display ram data corresponds to one dot of lcd. normal display and reverse display by rev register are set up as follows. normal display (rev = 0) : ram data = "0"; not lighted ram data = "1"; lighted reverse display (rev = 1) : ram data = "0"; lighted ram data = "1"; not lighted 2.8. segment display output order/ reverse set up the order of display outputs, seg 0 to seg 127 can be reversed by reversing access to display ram from mpu by using ref register, to lessen the limitation on placing ic when composing an lcd module.
LH155BA 18 2.9. relationship between display ram and address x address y address line address x = 0f h x = 00 h x = 0e h x = 01 h x = 00 h x = 0f h display starting line 0 1 ref 0 1 d 7 d 7 d 0 d 6 d 1 d 5 d 2 d 4 d 3 d 3 d 4 d 2 d 5 d 1 d 6 d 0 d 7 d 0 d 6 d 1 d 5 d 2 d 4 d 3 d 3 d 4 d 2 d 5 d 1 d 6 d 0 d 7 d 7 d 0 d 6 d 1 d 5 d 2 d 4 d 3 d 3 d 4 d 2 d 5 d 1 d 6 d 0 d 7 swap common output 00 h 01 h 02 h 03 h 04 h 05 h 06 h 07 h 08 h 09 h 0a h 0b h 0c h 0d h 0e h 0f h 00 h 01 h 02 h 03 h 04 h 05 h 06 h 07 h 08 h 09 h 0a h 0b h 0c h 0d h 0e h 0f h 37 h 38 h 39 h 3a h 3b h 3c h 3d h 3e h 3f h com 0 com 1 com 2 com 3 com 4 com 5 com 6 com 7 com 8 com 9 com 10 com 11 com 12 com 13 com 14 com 15 com 55 com 56 com 57 com 58 com 59 com 60 com 61 com 62 com 63 37 h 38 h 39 h 3a h 3b h 3c h 3d h 3e h 3f h seg 127 seg 126 seg 125 seg 124 seg 123 seg 122 seg 121 seg 120 seg 15 seg 14 seg 13 seg 12 seg 11 seg 10 seg 9 seg 8 seg 7 seg 6 seg 5 seg 4 seg 3 seg 2 seg 1 seg 0 segment output (configuration of display starting line address "00 h ")
19 LH155BA 2.10. display timing generator the display timing generator generates a timing clock necessary for internal operation and timing pulses (lp, flm, and m) by inputting the master clock ck or by the oscillation circuit of osci and osco. by setting up master/slave mode (m/s), the state of timing pulse pins and the timing generator changes. 2.11. signal generation to display line counter, and display data latching circuit both the clock to the line counter and latching signals to display data latching circuit from the display clock (lp) are generated. synchronized with the display clock, the line addresses of display ram are generated and 128- bit display data are latched to display-data latching circuit to output to the lcd drive circuit (seg output). readout of the display data to the lcd drive circuit is completely independent of mpu. therefore, a mpu that has no relationship the readout operation of the display data can access it. 2.12. generation of the alternating signal (m) and the synchronous signal (flm) lcd alternating signal (m) and synchronous signal (flm) are generated by the display clock (lp). the flm generates alternated drive waveform to the lcd drive circuit. normally, the flm generates alternated drive waveform every frame unit (m- signal level is reversed every one frame). but by setting up data (n e 1) in an n-line reverse register and n-line alternating command (nlin) at "h", n-line reverse waveform is generated. when the LH155BA is used in multi-chip, the signals of lp, flm, and m must be sent from master side in the slave operation. 2.13. display data latching circuit display data latching circuit temporally latches display data that is output display data to lcd drive circuit from display ram every one common period. normal display/reverse display, display on/off, and display all on commands are operated by controlling data in the latch. and no data within display ram changes. m/s pin mode lp pin m pin flm pin state of timing generator l slave input input input stop of lp, m, flm generation circuit h display timing pulse pins and timing generator state master output output output operating state
LH155BA 20 2.14. output timing of lcd driver 64 63 123 1 1 23 lp flm com 0 com 1 seg 0 seg 1 m v 4 v ss v ss v 1 v 1 v 2 v 1 v ss v 4 v 0 v 0 v 4 v 4 com 0 seg 0 seg 1 seg 2 com 1 64 v 1 v 4 v 3 v 0 v 2 v 2 v 3 v 0 v 2 v 3 v ss v 3 v 3 v ss 64 v 0 display timing at normal mode, 1/64 duty
21 LH155BA 2.15. lcd drive circuit this drive circuit generates 4 levels of lcd drive voltage. the circuit has 128 segment outputs and 64 common outputs and outputs combined display data and m signal. a common drive circuit that has a shift register sequentially outputs common scan signals. 2.16. oscillation circuit the frequency of this cr oscillator is controlled by the feedback resistor r f . the output from this oscillator is used as the timing signal source of the display and the boosting clock to the booster circuit. this is valid only in the master operation mode. during the slave operation mode, maintain osci pin at v ss and osco pin open (nc). when in the master operation mode and if external clock is used, maintain osci pin at v ss and osco pin open (nc), and feed the clock to ck pin. the duty cycle of the external clock must be 50%. the cks pin selects either internal oscillation circuit or external clock. 2.17. power supply circuit this circuit supplies voltages necessary to drive an lcd panel. this circuit is valid only in the master operation mode. the circuit consists of booster circuit and voltage converter. boosted voltage from the booster circuit is fed to the voltage converter which converts this high input voltage into v 0 , v 1 , v 2 , v 3 and v 4 which are used for graphic display. this internal power supply should not be used to drive a large lcd panel containing many pixels or a large lcd panel that has large capacity consisting of more than one chip. otherwise, display quality will degrade considerably. instead, use an external power supply. this internal power supply is controlled by the power supply circuit on/off command (pon). when the internal power supply is turned off, the booster circuit and voltage converter are also turned off. when using the external power supply, turn off the internal power supply, disconnect pins cap+, cape, v ee2 , v ee3 , v out , v ee , v r1 and v r2 , and keep pmode pin at v ss . then, feed external lcd drive voltages to pins v 0 , v 1 , v 2 , v 3 , and v 4 . this circuit can be changed by the state of pmode pin. notes : 1. because the booster circuit and voltage converter are not functioning, disconnect pins cap+, cape, v ee2 , v ee3 , v out , v ee , v r1 and v r2 . apply external lcd drive voltages to corresponding pins. 2. because the booster circuit is not functioning, disconnect pins cap+, cape, v ee2 , v ee3 and v ee . derive the voltage source to be supplied to the voltage converter from v out pin and then output lcd drive voltage to v r1 and v r2 pins. the voltage level at v r1 and v r2 pins must be v r2 2 v r1 2 v out . cks master mode osc external clock (ck) osc external clock (ck) l enabled disabled disabled disabled h disabled enabled disabled disabled slave mode pon pmode booster circuit voltage converter external voltage input note 0 0 disabled disabled v 0 , v 1 , v 2 , v 3 , v 4 1 0 1 disabled disabled v 0 , v 1 , v 2 , v 3 , v 4 1 1 0 enabled enabled e 1 1 disabled enabled v out , v r1 , v r2 2
LH155BA 22 2.18. booster circuit setting bs register, booster circuit multiple can be selected. placing capacitor c 1 across cap+ and cape, across v ee2 and v ss , across v ee3 and v ss and across v out and v ss boosts four times. placing capacitor c 1 across cap+ and cape, across v ee2 and v ss , across v out and v ss , and setting v ee3 to nc when boosting three times. placing c 1 across cap+ and cape, across v out and v ss , and setting v ee2 and v ee3 to nc when boosting two times. the boosted voltage is output to v out pin. since the booster circuit uses the clock derived from the internal oscillation circuit or external clock as the boosting clock, the internal oscillation circuit must be enabled, or if external clock is selected, it must be fed to ck pin. the output level at the v out pin does not exceed the recommended maximum operating voltage (14.0 v) when the voltage is boosted. if this value is exceeded, the operation of the LH155BA is not covered by warranty. when boosting four times and three times, placement of capacitor is as shown below. v ee = 1.8 v v ss = 0 v v out = 5.4 v when boosted three times v ee = 1.8 v v ss = 0 v v out = 7.2 v when boosted four times cap+ cap v ee2 v ee3 v out when boosted four times cap+ cap v ee2 v ee3 v out when boosted three times if charge up of lcd drive voltage is not successful, check capacity, voltage dependency and temperature characteristics of external capacitor, and select appropriate device. when charge up is unsuccessful, it is advisable to charge up lcd drive voltage step by step (x 2, x 3, x 4) by inputting software from external microcontroller.
23 LH155BA 2.19. voltage control circuit the boosted voltage at the v out pin is connected to the v r1 and v r2 pins and then the lcd drive voltages (v 0 , v 1 , v 2 , v 3 , and v 4 ) are generated via the voltage converter. the input level at the v r1 and v r2 must meet the electric potential condition of v r1 3 v r2 . the internal electronic volume divides the electric potential between the v r1 and v r2 into 16 segments. since the v r1 and v r2 pins have high input impedance, the input voltage levels at the v r1 and v r2 are determined by the resistance ratio of r 1 , r 2 , and r 3 . the current flowing between the v out and v ss pins is determined by the combined resistance of r 1 , r 2 , and r 3 . therefore, r 1 , r 2 , and r 3 must be selected in accordance with the above current as well as the input voltage levels at the v r1 and v r2 . the boosted voltage at the v out pin originates from the voltage supplied at the v ee pin. thus, the dc path current generated with r 1 , r 2 , and r 3 connected between the v out and v ss pins is supplied as current at the v ee pin. the electric current value, four times larger than the dc path current generated between the v out and v ss pins when the voltage is boosted four times, is added as supply current at the v ee pin (three times larger current is added for tripled voltage). take sufficient care that the input levels at the v r1 and v r2 pins do not fluctuate with external noise (connect capacitor c 3 ). 2.20. electronic volume the voltage converter incorporates an electronic volume, which allows the lcd drive voltage level v 0 to be controlled with a command and also allows the tone of lcd to be controlled. if 4-bit data is stored in the register of the electronic volume, one level can be selected among 16 voltage values for the lcd drive voltage v 0 . the voltage control range of the electronic volume is determined by the input voltage levels at the v r1 and v r2 . this means that the voltage range of (v r1 to v r2 ) for the graphic display voltage control circuit is the controllable voltage range of the electronic volume. the electric potential relation between the v r1 and v r2 pins must be v r1 3 v r2 . the input voltage levels at the v r1 and v r2 must be selected in accordance with the voltage levels to be obtained with the electronic volume. 2.21. lcd drive voltage generation circuit the voltage converter contains the voltage generation circuit. the lcd drive voltages other than v 0 , that is, v 1 , v 2 , v 3 and v 4 , are obtained by dividing v 0 through a resistor network. the lcd drive voltage from LH155BA is biased at 1/7 or 1/9 for the graphic display mode and at 1/3 (fixed) for the segment display mode. when using the internal power supply, connect a stabilizing capacitor c 2 to each of pins v 0 to v 4 . the capacitance of c 2 should be determined while observing the lcd panel to be used. in this case, connect a capacitor c 3 to stabilize input voltage to v r1 and v r2 . a value of c 3 can be defined selectively. c 3 c 3 r 3 r 2 r 1 v r1 v out LH155BA v r2 v ss c 1 example of voltage control circuit
LH155BA 24 v ss c 2 c 2 c 2 c 2 c 2 c 1 c 1 v ss r 3 r 2 r 1 c 3 v ss v ss c 3 v ss c 1 v ss c 1 when using the external power supply when using the internal power supply v dd v dd v dd v ee cap + cap e v ee2 v ee3 v out v r1 v r2 v ee cap + cap e v ee2 v ee3 v out v r1 v r2 v ss v 0 v 1 v 2 v 3 v 4 v a v b v c v d v a v b v c v d osci osco cks v dd v ss v 0 v 1 v 2 v 3 v 4 v a v b v c v d v 0 v 1 v 2 v 3 v 4 v a v b v c v d osci osco cks r f r f external power supply external power supply c 1 recommended values 1.0 to 5.0 f (b) * c 2 1.0 to 2.0 f (b) * c 3 0.01 to 0.1 f r f 680 k$ 2.22. example of power supply circuit connection 2.0 to 4.0 m$ r 1 + r 2 + r 3 * b characteristics must be used with c 1 and c 2 .
25 LH155BA 2.23. initialization the LH155BA is initialized by setting resb pin to "l". normally, resb pin is initialized together with mpu by connecting to the reset pin of mpu. when power is on, be sure to reset operation. 3. precautions precautions when connecting or disconnecting the power supply this ic may be permanently damaged by a high current which may flow if voltage is supplied to the lcd drive power supply while the logic system power supply is floating. the details are as follows. q when using an external power supply ? when connecting the power supply after connecting the logic system power supply, make reset operation and then apply external lcd drive voltages to corresponding pins. (v 0 , v 1 , v 2 , v 3 , v 4 or v out , v r1 and v r2 ) ? when disconnecting the power supply after executing halt command, disconnect external lcd drive voltages and then disconnect the logic system power supply. w when using the internal power supply ? when connecting the power supply after connecting the logic system power supply, make reset operation and then execute pon command. ? when disconnecting the power supply after executing halt command, disconnect the logic system power supply. it is advisable to connect the serial resistor (50 to 100 $) or fuse to the lcd drive power v out or v 0 of the system as a current limiter. set up a suitable value of the resistor in consideration of the display grade. parameter initial state display ram not fixed x-address 00 h set y-address 00 h set display starting line set at the first line (0 h ) display on/off display off display normal/reverse normal display duty 1/64 n-line alternating every frame unit common shift direction com 0 / com 63 increment mode increment off ref mode normal data swap mode off register in electronic volume (1, 1, 1, 1) power supply off
LH155BA 26 4. command function 4.1. command function table instruction code code function csb rs wrb rdb re d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 display data write 0 write data writes to display ram. display data read 0 0 1 0 0 read data reads from display ram. x address set [0 h ] 010100 sets x direction address in display ram. y address set (lower) [2 h ] 010100010 y address sets y direction address in display ram. y address set (upper) [3 h ] 010100011*y address sets y direction address in display ram. display starting line set (lower) [4 h ] 010100100 display starting line sets line address of ram making com 0 display. display starting line set (upper) [5 h ] 010100101** sets line address of ram making com 0 display. n-line alternating set (lower) [6 h ] 010100110 alternating line sets the number of alternating reverse line. n-line alternating set (upper) [7 h ] 010100111** sets the number of alternating reverse line. display control (1) set [8 h ] 0101 0 1000 shi ft seg on all on on/ off q display control (2) set [9 h ] 0 1001 re v nl in sw ap re f increment control set [a h ] 0 1 0 1 0 * aim ayi axi p ower control (1) set [b h ] 0 1011 bi as ha lt po n ac l p ower control (2) set [d h ] 0 1 1 0 1 dvol sets electronic volume for the graphic display. re set [f h ] 0 1111***re address set for internal register read 0 1100 address for register read sets address of internal register for reading. internal register read 0 * * * * read data reads out internal register. 0010 1010 1010 1010 1010 1 0 1 0/1 1010 1100 w aim : increment mode selection ayi : y increment, axi : x increment bias : 1/7 or 1/9, halt : halt on pon : power on, acl : reset sets re flag. 0 0 0 x address display starting line alternating line 1**erir er : segment's external source ir : segment source mode 0 1 0 1 e seg pon 0 1 1 1 0 p ower control (3) set [e h ] 1 duty du1 du0 * exa ic on duty : selects duty ratio. bs : selects boosted voltage level. bs1 bs0 q shift : common shift direction for the graphic display, segon : segment display on, allon : all graphic display on, on/off : graphic display on/off control w rev : graphic display normal/reverse, nlin : n- line reverse on, swap : data for graphic display swap, ref : segment output for graphic display normal/reverse e segpon : power supply for segment display (not available now. set to "0".), exa : clock for segment display external/internal, icon : icon display on * mark means "don't care". parenthesis [ ] shows address for internal register read.
LH155BA 27 the LH155BA has a lot of commands, as shown in the list of commands, and each command is explained in detail as follows. data codes and command codes are defined as follows and the execution of commands must be made in the chip selection state (csb = "l"). (for example x address) rs * command codes * rs = "0" : ram data access (refer to sections 4.2. and 4.3. .) rs = "1" : register access (refer to sections 4.4. through 4.17. .) the undefined command codes are inhibited. the display ram data of 8-bit are written in the designated x and y addresses. 4.2. data write to display ram the 8-bit contents of display ram designated in x and y addresses are read out. immediately after data are set in x and y addresses, dummy read is necessary one time. 4.3. data read to display ram d 4 0 d 5 0 d 6 0 d 7 0 ax0 d 0 ax1 d 1 ax2 d 2 ax3 d 3 data codes d 0 csb d 1 d 2 d 3 d 4 d 5 d 6 d 7 display ram write data d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 display ram read data re rdb wrb rs 0010 0 csb re rdb wrb rs 0100 0 (at the time of reset : ax3 to ax0 = 0 h , read address : 0 h ) 4.4. x address register set addresses of display ram's x direction are set. the values of ax3 to ax0 are usable up to 00 h - 0f h , but 10 h -ff h are inhibited. when the register setting of seg output normal/reverse is ref = "0", the data of ax3 to ax0 are addressed to display ram as they are. when ref = "1", the data of 0f h -(ax3 to ax0) h are addressed to the display ram. d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 0 0 0 0 ax3 ax2 ax1 ax0 csb re rdb wrb rs 1010 0
LH155BA 28 (at the time of reset : ay3 to ay 0 = 0 h , read address : 2 h ) 4.5. y address register set * mark means "don't care". (at the time of reset : ay6 to ay4 = 0 h , read address : 3 h ) addresses of display ram's y direction are set. in data-setting, lower place and upper place are divided with 4 bits and 3 bits respectively. when data are set, lower place should be set first and upper place should be set second. the values of ay6 to ay0 are usable up to 00 h - 42 h , but 43 h -ff h are inhibited. the addresses of 40 h to 42 h are for the segment display ram. (at the time of reset : la3 to la0 = 0 h , read address : 4 h ) 4.6. display starting line register set * mark means "don't care". (at the time of reset : la5, la4 = 0 h , read address : 5 h ) the display line address is required to designate, and the designated address becomes the display line of com 0 . the display of lcd is displayed from the designated display starting line address to the increment direction of the line address. la3 la2 la1 la0 line address 0 1 | 63 0 0 | 1 0 0 1 0 0 1 0 1 1 0 0 1 la4 0 0 1 la5 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 0 0 1 0 ay3 ay2 ay1 ay0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 0 0 1 1 * ay6 ay5 ay4 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 0 1 0 0 la3 la2 la1 la0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 0 1 0 1 * * la5 la4 csb re rdb wrb rs 1010 0 csb re rdb wrb rs 1010 0 csb re rdb wrb rs 1010 0 csb re rdb wrb rs 1010 0
LH155BA 29 (at the time of reset : n3 to n0 = 0 h , read address : 6 h ) 4.7. n-line alternating register set 4.8. alternating timing (1) at the time of n-line alternating off (in case of 1/64 duty display) * mark means "don't care". (at the time of reset : n5, n4 = 0 h , read address : 7 h ) the reverse line number of lcd alternated drive is required to be set in the register. the line number possible to be set is 2 to 64 lines. the values set up by the n-line alternating register become enabled when the n-line alternated drive command is on (nlin = "1"). when the n-line alternated drive command is off (nlin = "0"), an alternated drive waveform which reverses by frame cycle is generated. n3 n2 n1 n0 reverse line number e 2 | 64 0 0 1 0 0 | 1 0 0 1 0 1 1 1st line 2nd line 3rd line 64th line 1st line 2nd line lp flm m 0 0 1 n4 0 0 1 n5 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 0 1 1 0 n3 n2 n1 n0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 0 1 1 1 * * n5 n4 csb re rdb wrb rs 1010 0 csb re rdb wrb rs 1010 0
LH155BA 30 (2) at the time of n-line alternating on 1st line lp m 2nd line n-line alternate 3rd line n-th line 1st line 2nd line (at the time of reset : (shift, segon, allon, on/off) = 0 h , read address : 8 h ) * mark means "don't care". (at the time of reset : (er, ir) = 0 h , read address : 8 h ) various controls of display are set up. (1) on/off command (for the graphic display only) to control on/off of the graphic display. on/off = "0" : display off on/off = "1" : display on (2) allon command (for the graphic display only) regardless of the data of the graphic display ram, all the graphic displays are on. this command has priority over display normal/reverse commands. allon = "0" : normal display allon = "1" : all displays lighted. (3) segon command (for the segment display only) to control on/off of the segment display. segon = "0" : display off the pins are specified v ss level. segon = "1" : display on (4) shift command (for the graphic display only) the shift direction of the graphic display scanning data in the common drive output is selected. shift = "0" : com 0 / com 63 shift-scan shift = "1" : com 63 / com 0 shift-scan (1) ir command (for the segment display only) ir command is not available now. when using the segment display, set to "0". (2) er command (for the segment display only) er command is not available now. when using the segment display, set to "1". 4.9. display control (1) register set d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 1 0 0 0 shift segon allon on/off d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 1000**erir csb re rdb wrb rs 1010 0 csb re rdb wrb rs 1011 0
LH155BA 31 and when using the segment display, input v a , v b , v c and v d level externally. external power supply v a v b v c v d LH155BA d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 1 0 0 1 rev nlin swap ref 4.10. display control (2) register set (at the time of reset : (rev, nlin, swap, ref) = 0 h , read address : 9 h ) various controls of display are set up. (1) ref command when mpu accesses to the graphic display ram, the relationship between x address and write data is normalized or reversed. therefore, the order of segment drive output can be reversed by register setting, to lessen the limitation on placing ic when composing an lcd module. csb re rdb wrb rs 1010 0 ref access from mpu internal access corresponding seg output x address d 7 -d 0 x address d 7 -d 0 0n h d 0 (lsb) | d 7 (msb) n h (lsb) | (msb) seg (8 x n h ) output | seg (8 x n h + 7) output 1n h d 0 (lsb) | d 7 (msb) 0f h -n h (msb) | (lsb) seg (8 x (0f h e n h ) + 7) output | seg (8 x (0f h e n h )) output
LH155BA 32 (3) nlin command (for the graphic display only) the on/off control of n-line alternated drive is performed. nlin = "0" : n-line alternated drive off. by using frame cycle, the alternat- ing signals (m) are reversed. nlin = "1" : n-line alternated drive on. according to data set up in n-line alternating register, the alternation is made. (4) rev command (for the graphic display only) corresponding to the data of the graphic display ram, the lighting or not-lighting of the display is set up. rev = "0" : when ram data are at "h", lcd at on voltage (normal). rev = "1" : when ram data are at "l", lcd at on voltage (reverse). swap = "0" swap = "1" external data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 internal data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 (2) swap command (for the graphic display only) when data to the graphic display ram are written, the write data are swapped. swap = "0" : normal mode. in data-writing, the data of d 7 to d 0 can be written to the graphic display ram. swap = "1" : swap mode on. in data-writing, the swapped data of d 7 to d 0 can be written to the graphic display ram. ref access from mpu internal access corresponding segs output x address d 7 -d 0 y address d 7 -d 0 000 h d 0 (lsb) | d 7 (msb) 00 h d 0 (lsb) | d 7 (msb) d 0 / d 7 segs 0 / segs 7 001 h d 0 (lsb) | d 3 (msb) 01 h d 0 (lsb) | d 3 (msb) d 0 / d 3 segs 8 / segs 11 d 0 / d 7 segs 0 / segs 7 d 0 (lsb) | d 7 (msb) 00 h d 0 (lsb) | d 7 (msb) 0f h 1 d 0 / d 3 segs 8 / segs 11 d 0 (lsb) | d 3 (msb) 01 h d 0 (lsb) | d 3 (msb) 0e h 1 when using this command, outputs of segment display circuits are set as below. however the order of d 0 / d 7 are not changed. when ref = "1", set x address of segment display circuits described below. 00 h / 0f h 01 h / 0e h
LH155BA 33 4.11. increment control register set * mark means "don't care". (at the time of reset : (aim, ayi, axi) = 0 h , read address : a h ) the increment mode is set up when accessing the graphic display ram. (the graphic display ram only) by aim, ayi, and axi registers, the setting-up of increment operation/non-operation for the x- address counter and the y-address counter every write access or every read access to the graphic display ram is possible. in setting to this control register, the increment operation of address can be made without setting successive addresses for writing data or for reading data to the graphic display ram from mpu. after setting this register, be sure to set the x and y address registers. because it is not assuring the data of x and y address registers after setting increment control registers, the increment control of x and y addresses by aim, ayi and axi registers is as follows. q this is effective when subsequently writing and reading the successive address areas. w this is effective in the case that, after reading and writing the successive address areas for every address, the read data are modified to write. aim selection of increment timing reference 0 when writing to graphic display ram or reading from graphic display ram q 1 only when writing to graphic display ram (read modify) w csb re rdb wrb rs 1010 0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 1 0 1 0 * aim ayi axi
LH155BA 34 q regardless of aim, no increment for x and y addresses. w according to the setting-up of aim, increment or decrement for only x address. in accordance with the ref conditions of seg normal/reverse output setting register, x address becomes as follows. at ref = "0" (normal output), increment by loop of at ref = "1" (reverse output), decrement by loop of e according to the setting-up of aim, increment for only y address. regardless of ref, increment by loop of for y address. r according to the setting-up of aim, cooperative variation for x and y addresses. when the access of x address is made up to 0f h , y address increment occurs. at ref = "0" (normal output) vary in the above loops. at ref = "1" (reverse output) vary in the above loops. 0f h 00 h (x address) (y address) 00 h 3f h 00 h 0f h (x address) (y address) 00 h 3f h 00 h 3f h 0f h 00 h 00 h 0f h axi selection of increment address reference 0 increment is not made q 1 x and y addresses cooperative, automatic increment r ayi 0 1 0 1 x address automatic increment w 1 0 y address automatic increment e
LH155BA 35 4.12. power control (1) register set (at the time of reset : (bias, halt, pon, acl) = 0 h , read address : b h ) (1) acl command the internal circuit can be initialized. this command is enabled only at master operation mode. acl = "0" : normal operation acl = "1" : initialization on if the power control register is read out immediately after executing acl command (acl = 1), the d 0 bit is in the state of "1". therefore, if the reset operation is internally started, the d 0 bit becomes "0". in executing acl command, the internal reset signals are internally generated by using display master clock (oscillation by osci and osco, or clock input at ck pin). therefore, after executing acl command, allow a waiting period having at least a two-cycle portion of the master clock before the next processing is made. (2) pon command the internal power supply for the graphic display circuit is set on/off. pon = "0" : power supply for the graphic display circuit off pon = "1" : power supply for the graphic display circuit on at pon = "1", the booster circuit and voltage converter for the graphic display circuit function. in accordance with the setting conditions of pmode pin, the operation circuit part changes. see table in section 2.17. for details. (3)halt command the conditions of power-saving are set on/off by this command. halt = "0" : normal operation halt = "1" : power-saving operation when setting in the power-saving state, the supply current can be reduced to a value near to that of the standby current. the internal conditions at power-saving are as follows. (a) the oscillation circuit and power supply circuit are stopped. (b) the lcd drive is stopped, and outputs of the segment driver and common driver are v ss level. (c) the clock input from ck pin is inhibited. (d) the contents of the display ram data are maintained. (e) the operation mode maintains the command execution state before executing power- saving command. (4) bias command the internal bias value for the graphic display can be set by this command. bias = "0" : 1/9 bias bias = "1" : 1/7 bias (bias value for the segment display is 1/3 fixed.) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 1 0 1 1 bias halt pon acl csb re rdb wrb rs 1010 0
LH155BA 36 (at the time of reset : (dvol) = 0 h , read address : d h ) the lcd drive voltage v 0 output from the internal power supply circuit can be controlled and the display tone on the lcd can be also controlled. the lcd drive v 0 takes one out of 16 voltage values by setting a 4-bit data register. if the electronic volume is not used, specify (1, 1, 1, 1) in the 4-bit data register. after the LH155BA is reset, the 4-bit data register is automatically set to (1, 1, 1, 1). 4.13. power control (2) register set electronic volume for the graphic display. d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 1 1 0 1 msb 111111111 lsb csb re rdb wrb rs 1010 0 0000 | 1111 smaller | larger v 0 msb 111111111 lsb 4.14. power control (3) register set * mark means "don't care". (at the time of reset : (segpon, exa, icon) = 0 h , read address : e h ) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 1110 segpon * exa icon (1) icon command icon display on/off. icon = "0" : icon is off. icon = "1" : icon is on. see section 2.4.3. "icon display mode" for details. (2) exa command clock for icon display external/internal. exa = "0" : internal clock exa = "1" : external clock from exa pin (3) segpon command a power supply for the segment display is set on/off. segpon = "0" : power supply circuit is off. segpon = "1" : power supply circuit is on. segpon command is not available now. set segpon = "0". csb re rdb wrb rs 1010 0
37 LH155BA (at the time of reset : (du1, du0, bs1, bs0) = 0 h , read address : e h ) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 1 1 1 0 du1 du0 bs1 bs0 csb re rdb wrb rs 1011 0 * mark means "don't care". (at the time of reset : (re) = 0 h , read address : f h ) re command re = "0" : the power supply selection for the segment display, duty ratio selection and boosted voltage level selection cannot be accessed. re = "1" : the extended function is set. the power supply selection for the segment display, duty ratio selection and boosted voltage level selection can be accessed. d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 1111***re (1) bs command command for bias setting. select boost voltage level below. (2) duty command command for duty setting. select duty ratio below. do not set bs1 = "1", bs0 = "0". 4.15. re register set bs1 boosted voltage level 1 1 0 1 1 0 0 0 4 times 3 times 2 times prohibition when data set up in the internal registers are read out, set the read address allotted to each register by this command before executing the read command of the internal registers. for example, when the data of the command register in the display control (1) are read out, set the values of (ra3, ra2, ra1, and ra0 ) = 8 h . refer to the functional description of each command or the list of commands for the read address allotted to each command register. 4.16. address set for internal register read (at the time of reset : ( ra 3, ra 2, ra 1, ra 0) = c h ) du1 duty ratio 1 1 0 1 1 0 0 0 1/64 1/48 1/32 1/16 csb re rdb wrb rs 1 0 1 0/1 0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 1 1 0 0 ra3 ra2 ra1 ra0 csb re rdb wrb rs 1010 0 bs0 du0
LH155BA 38 * mark means "don't care". command for reading out the data of the internal registers. when this command is executed, the read address in the internal registers to be read must be preset. 4.17. internal register read d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 * * * * internal register read data csb re rdb wrb rs 1100 0
LH155BA 39 a state of function power (v dd e v ss , v ee e v ss ) off setting optional functions setting halt command (lcd drive output v ss level) wait 4.18. example of setting commands (1) initialization (3) power off power will be stable inputting reset operation end initialization setting optional functions setting power control wait power (v dd e v ss , v ee e v ss ) on setting optional functions setting electronic volume maximum setting bias ratio 1/7 (2) display data display data setting optional functions setting display on/off control end initialization setting optional functions setting electronic volume setting bias ratio setting display starting line setting increment control setting x address setting y address setting optional functions writing to display data if v dd and v ee voltages are not same, connect the logic system power supply (v dd ) first. if v dd and v ee voltages are not same, disconnect the booster circuit power supply (v ee ) first. after v ee , v out , v 0 , v 1 , v 2 , v 3 and v 4 voltages are below lcd on voltage (threshold voltage for liquid crystal turns on), disconnect the logic system power supply (v dd ).
LH155BA 40 5. absolute maximum ratings notes : 1. t a = +25 ?c 2. the maximum applicable voltage on any pin with respect to v ss (0 v). notes : 1. the applicable voltage on any pin with respect to v ss (0 v). 2. when using the booster circuit, power supply, v ee at the primary circuit must be used within the above-described range. if the drive voltage of lcd panel can be boosted by utilizing the voltage level of v dd , usually connect this pin to v dd power supply. 3. ensure that voltages are set such that v ss < v 4 < v 3 < v 2 < v 1 < v 0 . 4. the operating range is adjusted by the external circuit constructed between v out and v r1 , v r2 . the electric potential relation between the v r1 , v r2 and v out pins must be v r2 2 v r1 2 v out . 6. recommended operating conditions parameter symbol applicable pins rating unit note supply voltage (1) v dd v dd e0.3 to +6.0 v 1, 2 supply voltage (2) v ee v ee e0.3 to +6.0 v supply voltage (3) v out v out e0.3 to +15.0 v supply voltage (4) v r v r e0.3 to +15.0 v supply voltage (5) v 0 v 0 e0.3 to +15.0 v supply voltage (6) v 1 , v 2 , v 3 , v 4 v 1 , v 2 , v 3 , v 4 e0.3 to v 0 + 0.3 v input voltage v i d 7 -d 0 , csb, rs, m/s, m86, rdb, wrb, ck, cks, osci, lp, flm, m, sda, scl, p/s, resb, exa, pmode, test e0.3 to v dd + 0.3 v storage temperature t stg e45 to +125 ?c parameter symbol applicable pins min. typ. max. unit note supply voltage v dd v dd +1.8 +5.5 v 1 v ee v ee +2.4 +5.5 v 2 operating voltage v 0 v 0 +4.0 +14.0 v 3 v out v out +14.0 v v r1 , v r2 v r1 , v r2 +4.0 +14.0 v 4 operating temperature t opr e30 +85 ?c
41 LH155BA 7. electrical characteristics 7.1. dc characteristics (unless otherwise specified, v ss = 0 v, v dd = +1.8 to +5.5 v, t opr = e30 to +85 ?c) parameter symbol conditions applicable pins min. typ. max. unit note input "low" voltage v il d 7 -d 0 , csb, rs, m/s, m86, rdb, wrb, ck, cks, osci, lp, flm, m, sda, scl, p/s, resb, exa, pmode 0 0.2v dd v input "high" voltage v ih 0.8v dd v dd v output "low" voltage v ol i ol = 0.4 ma d 7 -d 0 , lp, flm, m 0.4 v output "high" voltage v oh i oh = e0.4 ma v dd e 0.4 v input leakage current i li v i = v ss or v dd csb, rs, m/s, m86, rdb, wrb, ck, cks, osci, sda, scl, p/s, resb, exa, pmode e10 10 a output leakage current i lo v i = v ss or v dd d 7 -d 0 , lp, flm, m e10 10 a 1 lcd drive output on resistance r on |?v on | = 0.5 v v 0 = 10 v seg 0 -seg 127 , com 0 -com 63 4 k$ 2 v 0 = 6 v standby current i stb ck = 0 v csb = v dd v dd 20 a 3 supply current (1) i dd1 during sleep mode v dd 20 a 4 reset ("l") pulse width t rw resb 10 s notes : 1. applied when d 7 to d 0 , lp, flm, and m are in the high impedance state. 2. resistance when 0.5 v is applied between each output pin and each power supply (v 0 , v 1 , v 2 , v 3 , v 4 ). applied when power is supplied at power bias ratio of 1/9 in the external power supply mode. 3. current at the v dd pin when the master clock stops, the chip is not selected (csb = v dd ), and no load is used. all circuits stop. 4. sleep mode supply current. stop internal oscillation clock, using external exa signal. without using booster circuits. graphic and segment displays off. icon display on. no load. 5. applied when no access is made by the mpu when the internal oscillation circuit (r f = 680 k$) and power supply circuit (pmode = "l") are used. the electronic volume is preset (the code is "1 1 1 1"). the display is off and the lcd drive pin is not loaded. measuring conditions : v dd = v ee , v r1 = v r2 , c 1 = c 2 = 1 f, r 1 + r 2 + r 3 = 4 m$. 6. active mode supply current. using internal oscillation clock. writing at f cyc the graphic display data which are reversed every one bit. no load. 7. oscillation frequency when connecting a feedback resistor (r f ) of 680 k$ between osci and osco. 6 v dd = 5 v v dd = 3 v v dd = 2 v 10 5 v dd = 5 v v dd = 3 v v dd = 2 v 10 5 80 120 v dd = 2 v v dd = 3 v v dd = 5 v 5 a 240 v dd , v ee during hold mode i dd2 supply current (2) supply current (3) i dd3 during active mode fcyc = 100 khz v dd 1 200 a 6 v dd = 5 v v dd = 3 v v dd = 2 v 400 200 24 28 v dd = 2 v v dd = 3 v v dd = 5 v 7 khz 30 osco r f = 680 k$2% f osc oscillation frequency
LH155BA 42 7.2. ac characteristics 7.2.1. system bus read/write timing (80-family mpu) (write timing) (read timing) t as8 t ah8 t wrw8 t dh8 t ds8 t cyc8 csb rs wrb d 7 -d 0 t as8 t ah8 t rdw8 t rdh8 t rdd8 t cyc8 csb rs rdb d 7 -d 0
LH155BA 43 (80-family mpu timing characteristics) (v dd = 2.7 to 5.5 v, t opr = e30 to +85 ?c) parameter symbol conditions applicable pins min. max. unit address hold time t ah8 csb rs 60 ns address setup time t as8 40 ns system cycle time t cyc8 rdb wrb 450 ns read pulse width (read) t rdw8 270 ns write pulse width (write) t wrw8 100 ns data setup time t ds8 d 7 -d 0 100 ns data hold time t dh8 40 ns read data output delay time t rdd8 c l = 15 pf d 7 -d 0 220 ns read data hold time t rdh8 10 ns input signal rise and fall time t r , t f all of above pins 15 ns (v dd = 2.4 to 2.7 v, t opr = e30 to +85 ?c) parameter symbol conditions applicable pins min. max. unit address hold time t ah8 csb rs 80 ns address setup time t as8 80 ns system cycle time t cyc8 rdb wrb 900 ns read pulse width (read) t rdw8 500 ns write pulse width (write) t wrw8 200 ns data setup time t ds8 d 7 -d 0 200 ns data hold time t dh8 80 ns read data output delay time t rdd8 c l = 15 pf d 7 -d 0 320 ns read data hold time t rdh8 10 ns input signal rise and fall time t r , t f all of above pins 30 ns (v dd = 1.8 to 2.4 v, t opr = e30 to +85 ?c) parameter symbol conditions applicable pins min. max. unit address hold time t ah8 csb rs 160 ns address setup time t as8 160 ns system cycle time t cyc8 rdb wrb 1 800 ns read pulse width (read) t rdw8 1 000 ns write pulse width (write) t wrw8 400 ns data setup time t ds8 d 7 -d 0 400 ns data hold time t dh8 160 ns read data output delay time t rdd8 c l = 15 pf d 7 -d 0 640 ns read data hold time t rdh8 10 ns input signal rise and fall time t r , t f all of above pins 30 ns note : all the timings must be specified relative to 20% and 80% of v dd voltage.
LH155BA 44 7.2.2. system bus read/write timing (68-family mpu) (write timing) (read timing) t cyc6 t ew6 t as6 t dh6 t ds6 e r/w csb rs d 7 -d 0 t ah6 t cyc6 t ew6 t as6 t rdd6 t rdh6 t ah6 e r/w csb rs d 7 -d 0
LH155BA 45 (68-family mpu timing characteristics) (v dd = 2.7 to 5.5 v, t opr = e30 to +85 ?c) parameter symbol conditions applicable pins min. max. unit address hold time t ah6 csb rs 60 ns address setup time t as6 40 ns system cycle time t cyc6 e 450 ns enable pulse width (read) t ew6 270 ns enable pulse width (write) 100 ns data setup time t ds6 d 7 -d 0 100 ns data hold time t dh6 40 ns read data output delay time t rdd6 c l = 15 pf d 7 -d 0 220 ns read data hold time t rdh6 10 ns input signal rise and fall time t r , t f all of above pins 15 ns (v dd = 2.4 to 2.7 v, t opr = e30 to +85 ?c) (v dd = 1.8 to 2.4 v, t opr = e30 to +85 ?c) parameter symbol conditions applicable pins min. max. unit address hold time t ah6 csb rs 80 ns address setup time t as6 80 ns system cycle time t cyc6 e 900 ns enable pulse width (read) t ew6 500 ns enable pulse width (write) 200 ns data setup time t ds6 d 7 -d 0 200 ns data hold time t dh6 80 ns read data output delay time t rdd6 c l = 15 pf d 7 -d 0 320 ns read data hold time t rdh6 10 ns input signal rise and fall time t r , t f all of above pins 30 ns parameter symbol conditions applicable pins min. max. unit address hold time t ah6 csb rs 160 ns address setup time t as6 160 ns system cycle time t cyc6 e 1 800 ns enable pulse width (read) t ew6 1 000 ns enable pulse width (write) 400 ns data setup time t ds6 d 7 -d 0 400 ns data hold time t dh6 160 ns read data output delay time t rdd6 c l = 15 pf d 7 -d 0 640 ns read data hold time t rdh6 10 ns input signal rise and fall time t r , t f all of above pins 30 ns note : all the timings must be specified relative to 20% and 80% of v dd voltage.
LH155BA 46 7.2.3. serial interface timing t css csb rs scl sda t csh t ahs t ass t dss t dhs t shw t slw t cycs (v dd = 2.4 to 5.5 v, t opr = e30 to +85 ?c) parameter symbol conditions applicable pins min. max. unit serial clock period t cycs scl 1 000 ns scl "h" pulse width t shw 400 ns scl "l" pulse width t slw 400 ns address setup time t ass rs 80 ns address hold time t ahs 80 ns data set up time t dss sda 400 ns data hold time t dhs 400 ns csb to scl time t css csb 80 ns csb hold time t csh 80 ns input signal rise and fall time t r , t f all of above pins 30 ns (v dd = 1.8 to 2.4 v, t opr = e30 to +85 ?c) parameter symbol conditions applicable pins min. max. unit serial clock period t cycs scl 2 000 ns scl "h" pulse width t shw 800 ns scl "l" pulse width t slw 800 ns address setup time t ass rs 160 ns address hold time t ahs 160 ns data set up time t dss sda 800 ns data hold time t dhs 800 ns csb to scl time t css csb 160 ns csb hold time t csh 160 ns input signal rise and fall time t r , t f all of above pins 30 ns note : all the timings must be specified relative to 20% and 80% of v dd voltage.
LH155BA 47 7.2.4. display control timing input timing characteristics (slave mode) (v dd = 2.4 to 5.5 v, t opr = e30 to +85 ?c) lp flm m t dm t dflm t dflm t lplw t lphw parameter symbol conditions applicable pins min. max. unit lp "h" pulse width t lphw lp 80 s lp "l" pulse width t lplw 80 s flm delay time t dflm flm e1.0 1.0 s m delay time t dm m e1.0 1.0 s input signal rise and fall time t r , t f all of above pins 15 ns (v dd = 1.8 to 2.4 v, t opr = e30 to +85 ?c) parameter symbol conditions applicable pins min. max. unit lp "h" pulse width t lphw lp 80 s lp "l" pulse width t lplw 80 s flm delay time t dflm flm e1.0 1.0 s m delay time t dm m e1.0 1.0 s input signal rise and fall time t r , t f all of above pins 30 ns output timing characteristics (master mode) (v dd = 2.4 to 5.5 v, t opr = e30 to +85 ?c) parameter symbol conditions applicable pins min. max. unit flm delay time t dflm c l = 15 pf flm 10 1 000 ns m delay time t dm 10 1 000 ns m (v dd = 1.8 to 2.4 v, t opr = e30 to +85 ?c) note : all the timings must be specified relative to 20% and 80% of v dd voltage. parameter symbol conditions applicable pins min. max. unit flm delay time t dflm c l = 15 pf flm 10 2 000 ns m delay time t dm 10 2 000 ns m
LH155BA 48 7.2.5. master clock input timing (v dd = 2.4 to 5.5 v, t opr = e30 to +85 ?c) t ckhw t cklw ck parameter symbol conditions applicable pin min. max. unit ck "h" pulse width t ckhw ck 10 32 s ck "l" pulse width t cklw 10 32 s input signal rise and fall time t r , t f 15 ns (v dd = 1.8 to 2.4 v, t opr = e30 to +85 ?c) parameter symbol conditions applicable pin min. max. unit ck "h" pulse width t ckhw ck 10 32 s ck "l" pulse width t cklw 10 32 s input signal rise and fall time t r , t f 30 ns note : all the timings must be specified relative to 20% and 80% of v dd voltage. 8. connection examples of representative applications (a) connection to the 80-family mpu a 0 a 7 -a 1 ? d 7 -d 0 t ? ? rs csb d 7 -d 0 rdb wrb resb decoder 7 8 reset input (80-family mpu) v cc gnd (LH155BA) v dd 1.8 to 5.5 v v ss
LH155BA 49 (b) connection to the 68-family mpu a 0 a 15 -a 1 vma d 7 -d 0 e r/ ? rs csb d 7 -d 0 rdb (e) wrb (r/w) resb decoder 15 8 reset input (68-family mpu) v cc gnd (LH155BA) v dd 1.8 to 5.5 v v ss (c) connection to the mpu with serial interface a 0 a 7 -a 1 port 1 port 2 ? rs csb sda scl resb decoder 7 reset input (mpu) v cc gnd (LH155BA) v dd 1.8 to 5.5 v v ss * when connecting multiple LH155BAs, input to each csb pin by varying the decoder conditions of address signals.
packages for lcd drivers 50 vss v4 v3 v2 v1 v0 test resb csb rs m/s m86 p/s sda scl wrb rdb d0 d1 d2 d3 d4 d5 d6 d7 flm m vss osco osci vss ck cks exa pmode vdd vee cape cap+ svr svout vee2 vee3 vout vr1 vr2 vc vb va vd dummy dummy dummy dummy pattern side (backside pi) (hole) total backside (sr) (hole) dummy dummy com62 com63 com32 com33 seg125 seg126 seg127 dummy dummy icon1 segs1 segs0 coms2 coms1 coms0 icon2 seg2 seg1 seg0 com0 com1 com31 com30 segs11 segs10 flexible slit 1.4 2.0 (sr) 8.1 0.6 (sl) 1.42 4.75 0.2 2-r0.7 2-r1.0 19.0 0.5 0.75 max. 1.1 max. 0.2 max. 6.8 4.5 [1.65] 2.0 (sl) 3.0 (sl) 3.6 7.8 0.5 10.4 (sr) [4.5] 4.2 (sr) 11.9 0.05 [12.9] [19.9] [7.0] 7.8 7.8 [0.5] 0.6 0.02 0.4 0.02 0.6 0.02 0.4 0.02 [0.8] 12.7 (sl) 8.85 (sl) device center film center chip center sprocket center (good device hole) 2.0 [2.5 typ. (2.2 min. )] 48.175 44.86 [35.3] 34.3 (sl) 14.4 (sl) p0.6 x (55 e 1) = 32.4 0.04 w0.3 0.02 30.0 0.05 (holes) 19.4 max. (resin area) 39.8 (backside pi) 39.2 (sl) p0.18 x (213 e 1) = 38.16 0.05 w0.09 [41.0] 39.5 0.05 (resin area) 5.62 max. 1.42 lp LH155BA5 tape width ? tape specification ? tape material 48 mm tape type super wide perforation pitch 5 pitches substrate upilex s75 adhesive #7100 cu foil [thickness] vlp 25 m solder resist polyimide ssf upilex is a trademark of ube industries, ltd.. 9. packages (unit : mm)
packages for lcd drivers 51 total backside pattern side vd seg125 seg126 seg127 com32 com33 seg2 seg1 seg0 com0 com1 icon2 coms0 coms1 coms2 segs0 segs1 segs10 segs11 com31 com30 com62 com63 icon1 va vb vc vr2 vr1 vout vee3 vee2 svout svr cap+ cape vee vdd pmode exa cks ck vss osci osco vss m flm d7 d6 d5 d4 d3 d2 d1 d0 rdb wrb scl sda p/s m86 m/s rs csb resb test v0 v1 v2 v3 v4 vss dummy dummy dummy dummy dummy dummy dummy dummy 2.0 (cu) 2.0 2.1 (sr) 1.8 (hole) 1.5 (hole) 0.4 0.02 0.2 max. 0.2 r1.05 (sr) 7.0 0.05 28.0 0.06 4.8 (sr) 5.1 9.0 (sr) 2.0 (sl) 11.3 0.05 10.6 0.05 0.26 0.02 0.2 0.02 0.7 0.2 0.02 0.7 [1.0] 1.981 0.05 4.75 0.05 1.981 0.05 0.75 max. 1.1 max. 0.4 0.05 (hole) [3.7 (e.l.)] [0.5 (e.l.)] [7.7 (e.l.)] [12.3 (e.l.)] [20.0 (e.l.)] 7.0 0.7 27.0 0.7 device center film center chip center sprocket center 5.62 max. (resin area) 63.949 0.12 lp [47.6 (e.l.)] 45.6 (sl) p0.8 x (55 e 1) = 43.2 0.07 w0.4 19.4 max. (resin area) 39.0 0.08 (holes) p0.25 x (209 e 1) = 52.0 0.07 w0.13 p0.25 x (213 e 1) = 53.0 0.07 w0.13 54.4 0.075 [56.0 (e.l.)] r0.75 (hole) (good device hole) LH155BAf tape width ? tape specification ? tape material 70 mm tape type wide perforation pitch 5 pitches substrate upilex s75 adhesive e type cu foil [thickness] vlp 25 m solder resist epoxy resin

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